ZeroConnect

Hardware compressed memory IP for CXL devices and chip-to-chip links. Ultra-fast inline compression and decompression with complete, real-time compressed memory management.

What it does

ZeroConnect expands the memory capacity of CXL devices using hardware-accelerated inline compression, and it manages that compressed memory in real time. It is transparent to the host: it operates on the data requests and responses the host issues over CXL.mem, with explicit control available over CXL.io off the critical path.

At a glance

CXL Type 3 devices (SLD, MH-MLD)
Transparent to host over CXL.mem
LZ4 + ZeroDelta algorithms
Complete compressed memory management
RAS support with ECC and poison handling

A complete IP stack, not just a compressor

Shipping compressed memory takes far more than a compression engine. ZeroConnect delivers the full subsystem:

Compression and decompression, with two algorithm families by default.
Hardware address remapping from device to media address space.
On-chip block cache in SRAM for write aggregation and read caching, with ECC.
Compressed memory manager for allocation, de-allocation, and defragmentation.
Capacity backpressure with configurable watermarks and host interrupts.
Real-time telemetry for capacity and compression statistics.

Algorithms

Two families by default: LZ4 (open standard, fully block-format compliant) and ZeroDelta, the ZeroPoint proprietary algorithm tuned for very low, deterministic latency on the inline CXL path. Compaction is aligned to the 4KB page requirement.

Value proposition: reduce data center total cost of ownership by more than 15% by getting more usable capacity from the same memory.

Key specifications

Detailed area, SRAM, and cycle-level latency figures are configuration dependent.

CXL device target	CXL Type 3 devices: SLD and (MH-)MLD.
Host exposure	Transparent over CXL.mem. Explicit control via CXL.io (non-critical path).
Algorithms	LZ4 (open standard) and ZeroDelta (proprietary), at 32B / 64B granularity, grouped into 1KB or 4KB superblocks.
IP clock	Default 1.2 GHz. LZ4 up to 1.6 GHz; ZeroDelta up to 2 GHz.
Compression ratio	2–3x on general server workloads. By benchmark: TPC-H database 2x; db-shootout 2.5x; HPCG 2.3x; Spark/Scala-means 2.9x.
Read latency	Meets the OCP CXL budget of under 250 ns average read latency. Typically 70 ns including DRAM latency.
Block cache hit ratio	Greater than 90% across benchmarks.
Metadata overhead	Approximately 0.78% of DRAM media for address translation.
Cache / remapper area	Configurable. Typically 16 MB block cache / 128 KB remapper.
Data interface	AXI5, 256-bit / 512-bit. Configuration interface: AXI4, 64-bit.
CXL compliance	CXL 2.0 and CXL 3.1 TE, MH-MLD, RAS. Compatible with CXL 3.1 TSP security (range-based encryption).
RAS	SECDED ECC on all SRAMs, data poisoning, FW interrupts, and event logging.

What's included

Soft IP for CXL device ASICs: RTL and test framework.
Firmware running on the CXL device.
Host-based software driver to expose the OCP interface.
Integration support.

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